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<H1>4.1  Systems Registers</H1>
The registers designed for use by systems programmers fall into these
classes:
<UL>
<LI>EFLAGS
<LI>Memory-Management Registers
<LI>Control Registers
<LI>Debug Registers
<LI>Test Registers
</UL>
<H2>4.1.1  Systems Flags</H2>
The systems flags of the EFLAGS register control I/O, maskable interrupts,
debugging, task switching, and enabling of virtual 8086 execution in a
protected, multitasking environment. These flags are highlighted in 
<A HREF="s04_01.htm#fig4-1">Figure 4-1</A>
  .
<DL>
<DT>
IF 
(Interrupt-Enable Flag, bit 9)
<DD>
Setting IF allows the CPU to recognize external (maskable) interrupt
requests. Clearing IF disables these interrupts. IF has no effect on
either exceptions or nonmaskable external interrupts . Refer to 
<A HREF="c09.htm">Chapter 9</A>
   for more details about interrupts .
<DT>
NT 
(Nested Task, bit 14)
<DD>
The processor uses the nested task flag to control chaining of
interrupted and called tasks. NT influences the operation of the 
<A HREF="IRET.htm">IRET</A>
instruction . Refer to 
<A HREF="c07.htm">Chapter 7</A> and 
<A HREF="c09.htm">Chapter 9</A>
for more information on
nested tasks.
<DT>
RF 
(Resume Flag, bit 16)
<DD>
The RF flag temporarily disables debug exceptions so that an instruction
can be restarted after a debug exception without immediately causing
another debug exception . Refer to 
<A HREF="c12.htm">Chapter 12</A>
   for details .
<DT>
TF 
(Trap Flag, bit 8)
<DD>
Setting TF puts the processor into single-step mode for debugging. In
this mode, the CPU automatically generates an exception after each
instruction, allowing a program to be inspected as it executes each
instruction. Single-stepping is just one of several debugging features of
the 80386 . Refer to 
<A HREF="c12.htm">Chapter 12</A>
   for additional information .
<DT>
VM 
(Virtual 8086 Mode, bit 17)
<DD>
When set, the VM flag indicates that the task is executing an 8086
program . Refer to 
<A HREF="c14.htm">Chapter 14</A>
   for a detailed discussion of how the 80386
executes 8086 tasks in a protected, multitasking environment.
</DL>

<A NAME="fig4-1">
<PRE>Figure 4-1.  System Flags of EFLAGS Register</PRE>
<P>
<PRE>
      31              23               15                7           0
     +---------------+-----------+-+-+++-+----+-+-+-+-+++-+-+-+-+-+-+-+
     |###########################|V|R|#|N|ID  |O|D|I|T|S|Z|#|A|#|P|#|C|
     |0 0 0 0 0 0 0 0 0 0 0 0 0 0| | |0| |    |#|#| |#|#|#|0|#|0|#|1|#|
     |###########################|M|F|#|T|  PL|F|F|F|F|F|F|#|F|#|F|#|F|
     +---------------+-----------+++++++++-+--+-+-+++-+++-+-+-+-+-+-+-+
                                  | |   |  |       |
             VIRTUAL 8086 MODE----+ |   |  |       |
                   RESUME FLAG------+   |  |       |
              NESTED TASK FLAG----------+  |       |
           I/O PRIVILEGE LEVEL-------------+       |
              INTERRUPT ENABLE---------------------+

----------------------------------------------------------------------------
NOTE
      0 OR 1 INDICATES INTEL RESERVED. DO NOT DEFINE.
----------------------------------------------------------------------------
</PRE>

<H2>4.1.2  Memory-Management Registers</H2>
Four registers of the 80386 locate the data structures that control
segmented memory management:
<DL>
<DT>
GDTR    
Global Descriptor Table Register
<DT>
LDTR    
Local Descriptor Table Register
<DD>
These registers point to the segment descriptor tables GDT and LDT.
Refer to 
<A HREF="c05.htm">Chapter 5</A>
   for an explanation of addressing via descriptor
tables.
<DT>
IDTR    
Interrupt Descriptor Table Register
<DD>
This register points to a table of entry points for interrupt handlers
(the IDT ) . Refer to 
<A HREF="c09.htm">Chapter 9</A>
   for details of the interrupt mechanism .
<DT>
TR      
Task Register
<DD>
This register points to the information needed by the processor to define
the current task . Refer to 
<A HREF="c07.htm">Chapter 7</A>
   for a description of the
multitasking features of the 80386.
</DL>

<H2>4.1.3  Control Registers</H2>

<A HREF="s04_01.htm#fig4-2">Figure 4-2</A>
  shows the format of the 80386 control registers CR0, CR2, and
CR3. These registers are accessible to systems programmers only via variants
of the <A HREF="MOV.htm">MOV</A> instruction, which allow them to be loaded from or stored in
general registers; for example:
<PRE>
MOV EAX, CR0
MOV CR3, EBX
</PRE>
CR0 contains system control flags, which control or indicate conditions
that apply to the system as a whole, not to an individual task.
<DL>
<DT>
EM 
(Emulation, bit 2)
<DD>
EM indicates whether coprocessor functions are to be emulated. Refer to

<A HREF="c11.htm">Chapter 11</A>
   for details .
<DT>
ET 
(Extension Type, bit 4)
<DD>
ET indicates the type of coprocessor present in the system (80287 or
80387 ) . Refer to 
<A HREF="c11.htm">Chapter 11</A> and 
<A HREF="c10.htm">Chapter 10</A> for details.
<DT>
MP 
(Math Present, bit 1)
<DD>
MP controls the function of the <A HREF="WAIT.htm">WAIT</A> instruction, which is used to
coordinate a coprocessor . Refer to 
<A HREF="c11.htm">Chapter 11</A>
   for details .
<DT>
PE 
(Protection Enable, bit 0)
<DD>
Setting PE causes the processor to begin executing in protected mode.
Resetting PE returns to real-address mode . Refer to 
<A HREF="c14.htm">Chapter 14</A>
   and

<A HREF="c10.htm">Chapter 10</A>
   for more information on changing processor modes .
<DT>
PG 
(Paging, bit 31)
<DD>
PG indicates whether the processor uses page tables to translate linear
addresses into physical addresses . Refer to 
<A HREF="c05.htm">Chapter 5</A>
   for a description
of page translation; refer to 
<A HREF="c10.htm">Chapter 10</A>
   for a discussion of how to set
PG.
<DT>
TS 
(Task Switched, bit 3)
<DD>
The processor sets TS with every task switch and tests TS when
interpreting coprocessor instructions . Refer to 
<A HREF="c11.htm">Chapter 11</A>
   for details .
</DL>
CR2 is used for handling page faults when PG is set. The processor stores
in CR2 the linear address that triggers the fault . Refer to 
<A HREF="c09.htm">Chapter 9</A>
   for a
description of page-fault handling.
<P>
CR3 is used when PG is set. CR3 enables the processor to locate the page
table directory for the current task . Refer to 
<A HREF="c05.htm">Chapter 5</A>
   for a description
of page tables and page translation.
<P>
<A NAME="fig4-2">
<PRE>Figure 4-2.  Control Registers</PRE>
<P>
<PRE>
 31                23                15                7               0
+-----------------+-----------------+--------+--------+-----------------+
|                                            |                          |
|    PAGE DIRECTORY BASE REGISTER (PDBR)     |         RESERVED         |CR3
|--------------------------------------------+--------------------------|
|                                                                       |
|                       PAGE FAULT LINEAR ADDRESS                       |CR2
|-----------------------------------------------------------------------|
|                                                                       |
|                                RESERVED                               |CR1
|-+-----------------------------------------------------------+-+-+-+-+-|
|P|                                                           |E|T|E|M|P|
|G|                              RESERVED                     |T|S|M|P|E|CR0
+-+---------------+-----------------+-----------------+-------+-+-+-+-+-+
</PRE>
<P>
<H2>4.1.4  Debug Register</H2>
The debug registers bring advanced debugging abilities to the 80386,
including data breakpoints and the ability to set instruction breakpoints
without modifying code segments . Refer to 
<A HREF="c12.htm">Chapter 12</A>
   for a complete
description of formats and usage.

<H2>4.1.5  Test Registers</H2>
The test registers are not a standard part of the 80386 architecture. They
are provided solely to enable confidence testing of the translation
lookaside buffer (TLB), the cache used for storing information from page
tables . 
<A HREF="c12.htm">Chapter 12</A>
   explains how to use these registers .
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